Unlock the full InfoQ experience by logging in! Stay updated with your favorite authors and topics, engage with content, and download exclusive resources. Birgitta Böckeler, Distinguished Engineer at ...

The emergence of SoC has been described as a development that will require fundamental changes in the approaches to design-for -testability (DFT). This will take the form of a “test re-use” strategy ...

Failures have been present in electronic products since the days of vacuum tubes, and despite enormous development and production improvements, no manufacturing technique can guarantee a 100% ...

For much of the lifetime of digital IC engineering, testability has been one of those issues that was somebody else's problem. But with the arrival of the SoC, it has become clear that testability ...

JTAG has its place but it is not by any means the total solution. Boundary scan, as standardized by IEEE 1149.1 and commonly referred to as JTAG, has truly revolutionized the testability of circuit ...

Many IC designers finally have embraced design for testability (DFT) in the form of scan insertion for digital circuit designs because of the significant time-to-production advantages these techniques ...

Hardware engineers employ all kinds of design reviews and processes, including design for manufacturability and design for testability. It's time software engineers stood up and asked for what they ...

The emergence of SoC has been described as a development that will require fundamental changes in the approaches to design-for -testability (DFT). This will take the form of a "test re-use" strategy ...