Hillsboro, Ore.—Lattice Semiconductor Corp. has released the LatticeECP2M FPGA family, consisting of low cost devices that offer high-speed embedded SerDes I/O plus a pre-engineered Physical Coding ...
Two core products, the 10 Gigabit Physical Coding Sublayer (PCS) and the Media Access Controller (MAC), are intended for use in Xilinx’s Virtex-II and Virtex-II Pro field programmable gate arrays ...
SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled the Cadence ® High-Speed Ethernet Controller IP family, which enables complete Ethernet subsystem ...
Physical Coding Sublayer (PCS) add-on to the successful MAC-1G controller provides new opportunities for an already wide range of possible implementations. Gliwice & Bielsko-Biala, Poland, June ...
Synopsys has released the first 1.6T Ethernet IP verification solution to meet the bandwidth demands of hyperscale data centers. The new multi-channel, multi-rate solutions include 1.6T MAC (Media ...
Ground Breaking Family Establishes New Price/Performance Standard for Low Cost, High Volume FPGAs HILLSBORO, OR - SEPTEMBER 18, 2006 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced ...
SANTA CLARA, Calif.--(BUSINESS WIRE)--The 25 Gigabit Ethernet Consortium, originally established to develop 25, 50 and 100 Gbps Ethernet specifications, announced today it has changed its name to the ...
Synopsys completed its acquisition of MorethanIP, a provider of Ethernet Digital Controller IP supporting data rates from 10G to 800G. The acquisition adds MAC (Medium Access Controller) and PCS ...
Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include ...
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